The present invention is generally directed to a data cache and method for use in a processing system of the type including at least one processor. The present invention is more particularly directed to such a data cache and method which provides for improved handling of errors encountered during attempted copy-back to external memory.
Data caches are well known in the art. Such caches are generally integrated with an associated processor for locally storing data required by the processor. Local storing of the data is advantageous because accesses by a processor to a local cache may be performed more quickly than accesses to external memory and because local accesses reduce the number of transactions which must be performed over an external memory bus.
In multi-processor systems which include a plurality of processors, each processor is generally integrated with an associated data cache. Each processor and data cache is coupled to external memory over a common memory bus.
When a processor of a multi-processor system writes new data into its local cache, the new data becomes "modified" with respect to the external memory and is so marked in the data cache. Even though such systems provide for consistency between the caches (some caches contain the same data), only the local cache receiving the new data marks the data as modified and is known as the "owner" of the data.
To further reduce the number of external memory accesses and to thereby maintain high processing performance, each cache performs a bus-watching function. If a processor associated with another cache issues a load instruction for requested data on the memory bus, and if a cache not associated with the requesting processor can provide the requested data, it will intervene before the external memory access and provide the requesting processor with the requested data over the memory bus. If no other cache intervenes, the external memory responds to provide the requested data over the memory bus.
Load instructions generally include lower order bits which form a multi-bit address and higher order bits which include a data identifier. Each storage location of each cache and of the external memory is assigned a unique address to permit the address bits to address the storage locations. Stored in each cache storage location, along with the data, is a multi-bit tag. When a cache receives a load instruction, either from its associated processor or over the memory bus from another cache, it compares the tag at the addressed storage location to the data identifier. If they match, the load instruction is said to "hit" in the cache and the cache can then supply the requested data. If the data identifier and the tag do not match, the load instruction is said to "miss" in that cache. If a load instruction misses in a local cache, the local cache then places the load instruction onto the memory bus to fetch the requested data from another cache or the external memory. If a load instruction received over the memory bus misses in a cache, that cache of course does not respond with data.
When a load instruction misses in a local cache, it is desirable for the local cache to fetch the requested data from the memory bus and store the data in the addressed storage location. This allows future load instructions for that memory location to be satisfied by the local cache without using the memory bus.
In addition to the data and the data tags stored in each cache storage location, each cache storage location also includes a validity bit to indicate if the stored data is valid and a modified bit to indicate if the stored data is modified. When a load instruction misses in a local cache, and the data stored in the addressed storage location is valid and modified, it is necessary to copy-back this data to the external memory before it is deleted. The simplest way to accomplish this replacement is to perform the copy-back to external memory before fetching the new data for the processor and storing the new data in the processor's local cache. However, in order to increase system performance, it has been more desirable to fetch the new data first to permit the processor to continue its executions and then to copy-back the valid and modified data while the processor continues to execute. To that end, data caches have also included a write buffer for temporarily storing the valid and modified data. This permits the new data to be provided to the processor and stored in the cache at the addressed storage location and the valid and modified data to then be copied-back to external memory. In accordance with at least one known processing system, the memory bus is held until the copy-back is completed.
A problem can arise, however, if an error is encountered during the copy-back process. Such an error may arise, for example, if the external memory is not able to accept the copied-back valid and modified data. One way to handle this situation is to leave the valid and modified data in the write buffer. However, this requires each cache to have the appropriate hardware to compare load instruction addresses to both the cache storage locations and the cache write buffer. Such hardware to perform this function is costly.